Digital logic circuits to build and simulate online

28 free guided builds — adders, subtractors, multiplexers, decoders, latches, flip-flops, counters and state machines — each built from logic gates in the BitForBytes Embedded Lab and checked automatically by simulating every row of its truth table or every clock cycle.

Adders

• Half adder — Add two bits: Sum = A ⊕ B, Carry = A · B — one XOR and one AND.
• Full adder — Two half adders and an OR: Sum = A ⊕ B ⊕ Cin, Cout = A·B + Cin·(A ⊕ B).
• 2-bit ripple-carry adder — Chain two full adders: the carry out of bit 0 ripples into bit 1.
• 2-bit carry-lookahead adder — Compute every carry at once from P = A ⊕ B and G = A · B, instead of waiting for it to ripple.
• 2-bit parallel-prefix adder — The black cell (G, P) ∘ (G′, P′) = (G + P·G′, P·P′) combines carries in a tree.
• Serial adder — One full adder and a D flip-flop that remembers the carry: add numbers one bit per clock, LSB first.

Subtractors

• Half subtractor — X − Y: Difference = X ⊕ Y, Borrow = X̄ · Y.
• Full subtractor — X − Y − Bin: two half subtractors and an OR.

Combinational

• 4-to-1 multiplexer — Two select lines choose which of four inputs reaches Y.
• 1-to-4 demultiplexer — The data bit D goes to the one output the select lines pick.
• 2-to-4 decoder — Two inputs select exactly one of four outputs.
• 4-to-2 priority encoder — The number of the highest input that is 1, in binary, plus V (valid).
• Binary to Gray code — Gray code changes one bit at a time: G3 = B3, and each other bit is the XOR of neighbours.
• NAND is universal — NOT, AND and OR — using nothing but NAND gates.
• Array-divider cell — One cell of a restoring array divider: subtract, then keep the old bit if the subtraction borrowed.
• Hazard-free SOP — F = A·B̄ + B·C glitches when B changes with A = C = 1; the consensus term A·C covers the gap.

Latches & flip-flops

• SR latch from NOR gates — Two cross-coupled NOR gates remember one bit: S sets it, R resets it.
• S̄R̄ latch from NAND gates — The NAND version is active-LOW: pull S̄ low to set, R̄ low to reset, both high to hold.
• JK flip-flop — Hold, set, reset and toggle — on the clock edge.
• Master–slave JK from latches — Two D latches on opposite clock phases make an edge-triggered flip-flop; D = J·Q̄ + K̄·Q makes it a JK.
• Turn a JK into a D flip-flop — J = D and K = D̄: the JK can then only set or reset, which is exactly a D flip-flop.

Counters & registers

• 4-bit shift register — Four D flip-flops in a chain: each clock moves every bit one place along.
• 3-bit ripple counter — Each T flip-flop toggles when the one before it falls: the count ripples up the chain.
• 3-bit synchronous counter — All flip-flops share one clock; AND gates decide who toggles: T0 = 1, T1 = Q0, T2 = Q0·Q1.
• 4-bit Johnson counter — A shift register whose last inverted output feeds the first: 8 states from 4 flip-flops.

State machines

• Analyse a clocked circuit — Build D = X ⊕ Q, then predict its state table before the checker runs it: it is a T flip-flop in disguise.
• "101" sequence detector — A Moore machine that raises Z after it has seen 1, 0, 1 on X (overlapping allowed).
• Up/down counter FSM — Design a 2-bit counter that counts up when U = 1 and down when U = 0 — the full FSM design flow.