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The full free BitForBytes curriculum in one place: digital system design, Verilog and basic electronics modules, plus 90+ hands-on labs and practice tools.

The first five Foundations modules are open without an account; a free account opens every other module and saves your progress.

Foundations

  1. Module 1: Signals & Waves
  2. Module 2: Number Systems
  3. Module 3: Logic Gates
  4. Module 4: Karnaugh Maps
  5. Module 5: Verilog Core

Basic Electronics

  1. Module 1: Physics of Control
  2. Module 2: Silicon, Doping & Carriers
  3. Module 3: The P-N Junction
  4. Module 4: Rectifiers & Filters
  5. Module 5: Special-Purpose Diodes
  6. Module 6: BJT Construction & Operation
  7. Module 7: BJT DC Biasing
  8. Module 8: BJT AC Analysis
  9. Module 9: MOSFET Construction
  10. Module 10: Transistors & JFETs

Digital System Design

  1. Module 1: Binary & Boolean Logic
  2. Module 2: K-Maps · Architect of Logic
  3. Module 3: Circuit Realisation
  4. Module 4: Practice Arena
  5. Module 5: Universal Gates
  6. Module 6: Combinational & Sequential Circuits
  7. Module 7: The Half Adder
  8. Module 8: The Full Adder
  9. Module 9: Recall & Prove
  10. Module 10: The Ripple-Carry Adder
  11. Module 11: The Carry Look-Ahead Adder
  12. Module 12: The Parallel Prefix Adder
  13. Module 13: The Serial Adder
  14. Module 14: Recall & Prime
  15. Module 15: How Computers Subtract
  16. Module 16: The Half Subtractor
  17. Module 17: The Full Subtractor
  18. Module 18: Complements
  19. Module 19: The 10's Complement
  20. Module 20: The BCD Adder
  21. Module 21: Multiplexer (MUX)
  22. Module 22: Demultiplexer (DEMUX)
  23. Module 23: Decoders
  24. Module 24: Encoders
  25. Module 25: Code Converters
  26. Module 26: Universal Logic & Shannon
  27. Module 27: Binary Dividers
  28. Module 28: Sequential Logic Fundamentals
  29. Module 29: Latches
  30. Module 30: Flip-Flops
  31. Module 31: Flip-Flop Timing & Race-Around
  32. Module 32: Flip-Flop Representations
  33. Module 33: Flip-Flop Conversions
  34. Module 34: Registers & Shift Registers
  35. Module 35: Ripple Counters
  36. Module 36: Synchronous Counters
  37. Module 37: Ring & Johnson Counters
  38. Module 38: Analysing Clocked Sequential Circuits
  39. Module 39: Mealy & Moore Machines
  40. Module 40: Designing State Machines
  41. Module 41: Asynchronous Sequential Circuits
  42. Module 42: Hazards & Races

Verilog Fundamentals

  1. Module 1: Modules & Ports
  2. Module 2: Lexical Rules & Number Literals
  3. Module 3: Data Types: Nets, Variables & Arrays
  4. Module 4: System Tasks & Compiler Directives
  5. Module 5: Wires & Registers (Wire vs Reg)
  6. Module 6: Gate-Level Primitives
  7. Module 7: Dataflow & RTL Modeling
  8. Module 8: Behavioural Modelling
  9. Module 9: Blocking vs Non-blocking
  10. Module 10: Conditionals & Latches
  11. Module 11: Vectors & Buses
  12. Module 12: Finite State Machines
  13. Module 13: Testbenches & Simulation
  14. Module 14: Hierarchy & Parameters
  15. Module 15: Counters & Shift Registers
  16. Module 16: Memories & Register Files
  17. Module 17: Tasks & Functions
  18. Module 18: Timing & Clock Domains
  19. Module 19: Design: Traffic Light Controller
  20. Module 20: Design: An 8-bit ALU
  21. Module 21: Design: UART Transmitter
  22. Module 22: Loops & Generate
  23. Module 23: Delays, Events & the Simulation Queue
  24. Module 24: Coding for Synthesis
  25. Module 25: Design: Synchronous FIFO
  26. Module 26: Design: Seven-Segment Display Driver
  27. Module 27: Operators in Full
  28. Module 28: Parallel Blocks & Procedural Control
  29. Module 29: User-Defined Primitives
  30. Module 30: Switch-Level Modelling
  31. Module 31: Timing Checks & specify Blocks
  32. Module 32: Simulation Output & File I/O
  33. Module 33: Project: UART Receiver
  34. Module 34: Project: SPI Master
  35. Module 35: Project: Debouncer & PWM
  36. Module 36: Project: LFSR & CRC
  37. Module 37: Project: Round-Robin Arbiter

SystemVerilog

  1. Module 1: SystemVerilog: What It Actually Is

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