FSM Synthesizer
Draw a Moore or Mealy state machine and watch it become a circuit, free and in your browser. Checks it for completeness and determinism, minimises the states, compares binary, Gray and one-hot encodings, shows the truth table and the minimised boolean equations, exports synthesizable Verilog, and proves the equations match your diagram with a SAT solver. This app needs JavaScript enabled. Explore:
VLSI Career Roadmap ·
Course Portal ·
Verilog Judge ·
K-Map Solver ·
Start Module 1