Verilog Judge: Practice Verilog Online

Write, run and auto-grade Verilog in your browser. A LeetCode-style judge for combinational and sequential logic to build RTL skills for VLSI interviews.

30 problems, each graded in the browser against test cases.

Easy

  1. Wire (basics, assign)
  2. NOT Gate (gates, assign)
  3. AND Gate (gates, assign)
  4. OR Gate (gates, assign)
  5. NAND Gate (gates, universal)
  6. NOR Gate (gates, universal)
  7. XOR Gate (gates, arithmetic)
  8. XNOR Gate (gates, equality)
  9. 3-Input AND (gates)
  10. 3-Input OR (gates)
  11. 3-Bit Parity (xor, parity)

Medium

  1. 2-to-1 Multiplexer (mux, select)
  2. Half Adder (arithmetic, multi-output)
  3. Majority Vote (logic, voting)
  4. Full Adder (arithmetic, multi-output)
  5. Half Subtractor (arithmetic)
  6. 4-to-1 Multiplexer (mux, select)
  7. 2-to-4 Decoder (decoder, multi-output)
  8. 1-Bit Comparator (comparator, multi-output)
  9. Binary → Gray (2-bit) (encoding, xor)
  10. 4-Bit Parity (xor, parity)
  11. D Flip-Flop (sequential, flip-flop, clocked)
  12. D Flip-Flop + Async Reset (sequential, flip-flop, reset)
  13. T Flip-Flop (sequential, flip-flop, toggle)

Hard

  1. Full Subtractor (arithmetic, multi-output)
  2. 2-Bit Comparator (comparator, multi-output)
  3. 2-Bit Adder (arithmetic, multi-output)
  4. 4-to-2 Priority Encoder (encoder, priority, multi-output)
  5. 1-Bit ALU (alu, select)
  6. JK Flip-Flop (sequential, flip-flop)

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