Up/down counter FSM: build and simulate it online
Design a 2-bit counter that counts up when U = 1 and down when U = 0 — the full FSM design flow.
Build the up/down counter fsm in the free online simulator — it checks your circuit automatically.
What you need
- 2 logic switches labelled U, CLK
- 2 probes labelled Q1, Q0
- 2 flip-flops
Step by step
- Inputs and outputs. From the Logic section of the library, drop digital inputs (0/1 boxes) or logic switches for the inputs, and digital outputs or probes for the outputs; give each its label in the inspector (the checker finds them by label). Switches U, CLK; Probes Q1, Q0
- State register. Two flip-flops hold Q1 Q0. D or T flip-flops — your choice.
- Next-state logic. With T flip-flops: T0 = 1, T1 = Q0 ⊙ U… work it out from the state table.
- Prove it. Up 0→1→2→3→0, then down 3→2.
Expected sequence
| # | inputs | clock | Q1 | Q0 |
|---|---|---|---|---|
| 1 | U=1 | ↑ | 0 | 1 |
| 2 | U=1 | ↑ | 1 | 0 |
| 3 | U=1 | ↑ | 1 | 1 |
| 4 | U=1 | ↑ | 0 | 0 |
| 5 | U=0 | ↑ | 1 | 1 |
| 6 | U=0 | ↑ | 1 | 0 |
Frequently asked questions
How do you build a up/down counter fsm?
Design a 2-bit counter that counts up when U = 1 and down when U = 0 — the full FSM design flow. In short: inputs and outputs, then state register, then next-state logic, then prove it.
How does a up/down counter fsm behave clock by clock?
It is checked over 6 steps: up → 1, up → 2, up → 3, up → 0, …. The table on this page shows the expected Q1, Q0 after each clock.
What parts do you need for a up/down counter fsm?
2 flip-flops — plus logic switches for the inputs and probes for the outputs.
Can I simulate a up/down counter fsm online for free?
Yes. Open it in the BitForBytes Embedded Lab, a free browser-based circuit and logic simulator: drag in the gates, wire them, and press "Check my circuit" — every clock cycle is simulated and marked for you. No download or sign-up needed.
Part of DSD 40 · State machine design in the free BitForBytes digital system design course.