S̄R̄ latch from NAND gates: build and simulate it online
The NAND version is active-LOW: pull S̄ low to set, R̄ low to reset, both high to hold.
Build the s̄r̄ latch from nand gates in the free online simulator — it checks your circuit automatically.
What you need
- 2 logic switches labelled SN, RN
- 2 probes labelled Q, QN
- 2 NAND gates
Step by step
- Inputs and outputs. From the Logic section of the library, drop digital inputs (0/1 boxes) or logic switches for the inputs, and digital outputs or probes for the outputs; give each its label in the inspector (the checker finds them by label). Switches SN, RN; Probes Q, QN
- Two NAND gates, cross-coupled. Q = NAND(SN, QN), QN = NAND(RN, Q).
- Prove it. Set, hold, reset, hold — all active LOW.
Expected sequence
| # | inputs | clock | Q | QN |
|---|---|---|---|---|
| 1 | SN=0 RN=1 | — | 1 | 0 |
| 2 | SN=1 RN=1 | — | 1 | 0 |
| 3 | SN=1 RN=0 | — | 0 | 1 |
| 4 | SN=1 RN=1 | — | 0 | 1 |
Frequently asked questions
How do you build a s̄r̄ latch from nand gates?
The NAND version is active-LOW: pull S̄ low to set, R̄ low to reset, both high to hold. In short: inputs and outputs, then two nand gates, cross-coupled, then prove it.
How does a s̄r̄ latch from nand gates behave clock by clock?
It is checked over 4 steps: set (S̄ low), hold 1, reset (R̄ low), hold 0. The table on this page shows the expected Q, QN after each clock.
What parts do you need for a s̄r̄ latch from nand gates?
2 NAND gates — plus logic switches for the inputs and probes for the outputs.
Can I simulate a s̄r̄ latch from nand gates online for free?
Yes. Open it in the BitForBytes Embedded Lab, a free browser-based circuit and logic simulator: drag in the gates, wire them, and press "Check my circuit" — every clock cycle is simulated and marked for you. No download or sign-up needed.
Part of DSD 41 · Asynchronous circuits in the free BitForBytes digital system design course.