Weekly Verilog Challenges for ECE Students
One small Verilog challenge every Wednesday, with hints on the page and the solution on Friday. Each challenge gives you the exact module spec, a truth table or waveform you can click through, starter code for the Verilog Sandbox and three hints that open one at a time.
- Challenge #2: Half Adder (
half_adder(a, b, sum, carry)): opens Wed, 7 Oct, 7:30 pm IST, solution Fri, 9 Oct, 6 pm IST. Build a half adder in Verilog: tap the truth table, spot the pattern in each output, then code it. - Challenge #3: Full Adder (
full_adder(a, b, cin, sum, cout)): opens Wed, 14 Oct, 7:30 pm IST, solution Fri, 16 Oct, 6 pm IST. Add three bits with a carry in: click the 8-row truth table, follow the carry, then write the Verilog. - Challenge #4: 4-to-1 Multiplexer (
mux4(d[3:0], sel[1:0], y)): opens Wed, 21 Oct, 7:30 pm IST, solution Fri, 23 Oct, 6 pm IST. Pick a select value and watch one input's path light up, then write a 4:1 mux in Verilog. - Challenge #5: D Flip-Flop with Enable and Reset (
dff_en(clk, rst_n, en, d, q)): opens Wed, 28 Oct, 7:30 pm IST, solution Fri, 30 Oct, 6 pm IST. Predict q before every clock edge on a clickable waveform, then build a DFF with async reset and enable.