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Verilog Challenge #3: Build a Full Adder

A full adder adds three 1-bit inputs, a, b and a carry in, and gives a 2-bit result: sum is the low bit and cout the high bit. Because it accepts the carry from the previous column, full adders chain together to add numbers of any width. You write full_adder(a, b, cin, sum, cout) in Verilog.

The module you will write: full_adder(a, b, cin, sum, cout)

  • a (input): first bit to add
  • b (input): second bit to add
  • cin (input): carry in, from the column to the right
  • sum (output): low bit of a + b + cin
  • cout (output): carry out, the high bit of a + b + cin

Where you'll use this

  • University exams: full adder truth table, K-map and circuit, often with a ripple-carry adder
  • Verilog RTL: chained full adders make the ripple-carry adder inside an ALU
  • Computer architecture: carry chains set how fast an adder can run
  • Interviews: "build a 4-bit adder" starts here

Key terms

Full adder
A circuit that adds three bits, two operands and a carry in, giving a sum bit and a carry out.
Carry in (cin)
The carry arriving from the less significant column.
Carry out (cout)
The carry leaving for the more significant column. It is 1 when the three inputs add up to 2 or 3.
Ripple-carry adder
Several full adders in a row, each one's carry out feeding the next one's carry in.
Hierarchy
Building a Verilog module out of instances of smaller modules.

Questions people ask

What will I build in the full adder challenge?

A Verilog module called full_adder with inputs a, b and cin and outputs sum and cout. The page has the exact spec, an 8-row clickable truth table, a circuit you can tap, starter code for the Verilog Sandbox and three hints that open one at a time.

When does the full adder challenge open?

It opens on Wednesday 14 October 2026 at 7:30 pm IST, alongside the WhatsApp group post. The worked solution, with the three most common mistakes, unlocks on Friday 16 October at 6 pm IST.

How is a full adder different from a half adder?

A half adder adds two bits and has no carry input. A full adder adds three bits, the third being the carry from the column to its right, so its total runs from 0 to 3. That carry input is what lets full adders be chained into a multi-bit adder.

Last updated · Reviewed by the BitForBytes team

When it opens

The challenge opens Wed, 14 Oct, 7:30 pm IST and the worked solution unlocks Fri, 16 Oct, 6 pm IST. It goes with Week 2's topic, Logic Gates, and Why NAND Can Build Everything.

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