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Verilog Challenge #5: D Flip-Flop with Enable and Reset

A D flip-flop with enable and reset stores one bit. At each rising clock edge it loads d only when en is 1, and otherwise keeps its value. An active-low asynchronous reset, rst_n, clears q to 0 at once, without waiting for the clock. You write dff_en(clk, rst_n, en, d, q) in Verilog.

The module you will write: dff_en(clk, rst_n, en, d, q)

  • clk (input): clock: q can change on its rising edge
  • rst_n (input): active-low asynchronous reset
  • en (input): enable: 1 loads d on the edge, 0 holds
  • d (input): data in
  • q (output): the stored bit

Where you'll use this

  • Verilog RTL: registers with a load enable sit in every CPU, FIFO and peripheral
  • State machines: the state register is a set of flip-flops with a reset
  • University exams: timing diagrams with clock, enable and reset
  • Interviews: synchronous vs asynchronous reset is a favourite question

Key terms

D flip-flop
A 1-bit memory that copies its D input to Q at the clock's rising edge.
Enable
A control input that decides whether the flip-flop loads new data on an edge or keeps its value.
Asynchronous reset
A reset that acts the moment it is asserted, without waiting for a clock edge.
Active-low
A signal that does its job when it is 0. Names often end in _n, as in rst_n.
Waveform
A plot of signals against time, used to check what a circuit does at each clock edge.

Questions people ask

What will I build in the D flip-flop challenge?

A Verilog module called dff_en with inputs clk, rst_n, en and d and an output q. The page has the exact spec, a waveform where you predict q before every clock edge, starter code for the Verilog Sandbox and three hints that open one at a time.

When does the D flip-flop challenge open?

It opens on Wednesday 28 October 2026 at 7:30 pm IST, alongside the WhatsApp group post. The worked solution, with the three most common mistakes, unlocks on Friday 30 October at 6 pm IST.

What is the difference between a synchronous and an asynchronous reset?

A synchronous reset is only acted on at a clock edge, so it behaves like any other input to the flip-flop. An asynchronous reset clears the flip-flop the moment it is asserted, even with the clock stopped, which is why it is used to bring a chip to a known state at power-up.

Last updated · Reviewed by the BitForBytes team

When it opens

The challenge opens Wed, 28 Oct, 7:30 pm IST and the worked solution unlocks Fri, 30 Oct, 6 pm IST. It goes with Week 4's topic, Latches vs Flip-Flops: Memory in Hardware.

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