Community › Week 4 · Building blocks
Latches vs Flip-Flops: How Hardware Remembers a Bit
A latch and a flip-flop both store one bit, but they listen at different times. A D latch is level-sensitive: while its enable is high, the output follows the input. A D flip-flop is edge-triggered: it copies the input only at the clock's rising edge and holds it until the next edge.
Where you'll use this
- University exams: characteristic tables, excitation tables and timing diagrams
- Verilog RTL: every register, counter and state machine you write becomes flip-flops
- Embedded systems: the control registers inside a microcontroller are banks of flip-flops
- Interviews: "latch vs flip-flop" and setup and hold time are asked in almost every VLSI round
Key terms
- Level-sensitive
- Responds for as long as a control signal is at a level, for example the whole time enable is 1.
- Edge-triggered
- Responds only at the instant a clock changes, usually from 0 to 1 (the rising edge).
- Rising edge
- The moment a clock goes from 0 to 1. Written posedge in Verilog.
- Setup time
- How long the input must be steady before the clock edge for the flip-flop to store it correctly.
- Hold time
- How long the input must stay steady after the clock edge.
- Register
- A group of flip-flops sharing one clock, storing a multi-bit value such as a byte.
Questions people ask
What is the difference between a latch and a flip-flop?
A latch is transparent while its enable is active, so any change on the input passes straight to the output. A flip-flop samples its input only at a clock edge and ignores it at every other moment. Both store one bit; they differ in when they listen.
Why do synchronous chips use flip-flops instead of latches?
Every flip-flop takes its sample at the same clock edge, so the logic between two flip-flops has a whole clock period to settle. Timing tools can check that simply. A latch stays open for part of the period, so a glitch can pass straight through it.
What are setup time and hold time?
Setup time is how long the input must be steady before the clock edge, and hold time is how long it must stay steady after it. Break either rule and the flip-flop can store the wrong value or hang between 0 and 1 for a while, which is called metastability.
Last updated · Reviewed by the BitForBytes team
When it opens
Part 1, the interactive concept, opens Mon, 26 Oct, 7:30 pm IST. Part 2, the harder half with worked Level-Up answers, opens Thu, 29 Oct, 7 pm IST. Both are free and need no signup.
This week's challenge
Challenge #5: D Flip-Flop with Enable and Reset: Predict q before every clock edge on a clickable waveform, then build a DFF with async reset and enable. Opens Wed, 28 Oct, 7:30 pm IST.