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Verilog Challenge #4: Build a 4-to-1 Multiplexer

A 4-to-1 multiplexer picks one of four data inputs and copies it to a single output, steered by a 2-bit select signal: select 0 passes d[0], 1 passes d[1], 2 passes d[2] and 3 passes d[3]. In this challenge you write mux4(d[3:0], sel[1:0], y) in Verilog and test every select value.

The module you will write: mux4(d[3:0], sel[1:0], y)

  • d[3:0] (input): four data inputs, d[0] to d[3]
  • sel[1:0] (input): which input to pass through, 0 to 3
  • y (output): the selected input

Where you'll use this

  • University exams: multiplexer truth tables and "implement a function using a mux" questions
  • Verilog RTL: every choice between values in a datapath becomes a mux
  • FPGAs: lookup tables and routing are built from multiplexers
  • Embedded systems: analog multiplexers share one ADC between several sensors

Key terms

Multiplexer (mux)
A data selector: several inputs, one output, and select lines that choose which input goes through.
Select lines
The control inputs of a mux. n select lines choose among 2^n inputs, so a 4-to-1 mux needs 2.
Bus
A group of wires treated as one multi-bit signal, such as d[3:0].
Vector
A multi-bit Verilog signal declared with a range, like input [3:0] d.
Demultiplexer
The reverse of a mux: one input routed to one of several outputs.

Questions people ask

What will I build in the 4-to-1 mux challenge?

A Verilog module called mux4 with a 4-bit input d, a 2-bit input sel and a 1-bit output y. The page has the exact spec, a circuit where the chosen path lights up, starter code for the Verilog Sandbox and three hints that open one at a time.

When does the 4-to-1 mux challenge open?

It opens on Wednesday 21 October 2026 at 7:30 pm IST, alongside the WhatsApp group post. The worked solution, with the three most common mistakes, unlocks on Friday 23 October at 6 pm IST.

Why does a 4-to-1 multiplexer need two select lines?

Each select line is one bit, and two bits have four patterns, 00, 01, 10 and 11, one for each input. In general a mux with n select lines can choose among 2 to the power n inputs, so an 8-to-1 mux needs three.

Last updated · Reviewed by the BitForBytes team

When it opens

The challenge opens Wed, 21 Oct, 7:30 pm IST and the worked solution unlocks Fri, 23 Oct, 6 pm IST. It goes with Week 3's topic, K-Maps: Simplify Logic by Drawing Boxes.

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