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Why Computers Count in Binary (and Write It in Hex)

Computers count in binary because a transistor is reliably either on or off, and two voltage levels are easy to tell apart even when the signal is noisy. Each bit is worth double the bit on its right: 1, 2, 4, 8 and so on. Hex packs four bits into one digit, so 0101 1010 is 0x5A, or 90.

Where you'll use this

  • University exams: decimal, binary, octal and hex conversions in every Digital Electronics paper
  • Verilog RTL: sized literals such as 8'h5A and 4'b1010 on every bus you write
  • Embedded C: register values and bit masks are written in hex
  • Interviews: quick conversions and "how many bits do you need?" questions

Key terms

Bit
One binary digit, 0 or 1. In hardware it is one wire that is either low or high.
LSB and MSB
The least significant bit is the rightmost one, worth 1. The most significant bit is the leftmost one, worth the most.
Nibble
A group of four bits. It has 16 patterns, so it is exactly one hex digit.
Hexadecimal
Base 16. The digits are 0 to 9, then A to F for 10 to 15. Written 0x5A in C and 8'h5A in Verilog.
Sized literal
A Verilog number that states its width and base, such as 8'h5A: eight bits, written in hex.

Questions people ask

Why don't computers use decimal?

A decimal circuit would have to tell ten voltage levels apart, and a little noise would turn one digit into the next. Two levels, high and low, leave a wide safety margin, so binary circuits are simpler, faster and far more reliable.

How do I convert decimal to binary by hand?

Divide by 2 again and again and write down each remainder, then read the remainders from the last one back to the first. For 13: 13 gives 6 r 1, 6 gives 3 r 0, 3 gives 1 r 1, 1 gives 0 r 1, so 13 is 1101. Check it by adding the weights: 8 + 4 + 1 = 13.

What does 8'hFF mean in Verilog?

It is an 8-bit number written in hexadecimal. The 8 is the width in bits, 'h says the digits are hex, and FF is the value, so the bits are 1111 1111, which is 255 when read as an unsigned number.

Last updated · Reviewed by the BitForBytes team

When it opens

Part 1, the interactive concept, opens Mon, 5 Oct, 7:30 pm IST. Part 2, the harder half with worked Level-Up answers, opens Thu, 8 Oct, 7 pm IST. Both are free and need no signup.

This week's challenge

Challenge #2: Half Adder: Build a half adder in Verilog: tap the truth table, spot the pattern in each output, then code it. Opens Wed, 7 Oct, 7:30 pm IST.

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