Scan Chain Lab: See DFT on Your Own Verilog

Write a sequential Verilog design and watch its flip-flops get stitched into a scan chain. Shift a pattern in, capture, and shift the response out.

Scan Chain Lab: Stitch a scan chain and shift a pattern through it, flop by flop. It runs in the browser, with nothing to install.

Related: architecture tools

How the hardware actually behaves.

• LeetCPU: Step a RISC-V pipeline cycle by cycle. Turn forwarding off and watch the stalls.
• FSM Synthesizer: Draw a state machine, get the encoding, the equations and synthesisable RTL.
• K-Map Lab: Minimise a truth table and see the prime implicants grouped.

More free tools

• Embedded Lab: Arduino, ESP32, Pico and STM32 simulator
• Digital Logic Lab: gates, flip-flops and counters
• Project guides
• Guided logic builds
• Verilog Judge
• Verilog practice problems
• Verilog Sandbox
• Karnaugh map solver
• FSM synthesizer
• VLSI career roadmap
• Interview preparation
• Retro Silicon Arcade