VerifCompiler — Generate a UVM Testbench from Verilog RTL

Paste a Verilog module and get the UVM environment around it: interface with clocking blocks, sequence item, driver, monitor, agent, scoreboard, covergroup and tb_top. Runs entirely in the browser, and reviews your RTL for latches, blocking assignments and reset bugs while it is on screen. This app needs JavaScript enabled. Explore:

VLSI Career Roadmap · Course Portal · Verilog Judge · K-Map Solver · Start Module 1