Verilog Build Projects — UART, Async FIFO, Cache and RISC-V Datapath

Free multi-stage RTL build projects: a UART transceiver, an asynchronous FIFO with clock domain crossing, an SPI master, a RISC-V integer datapath, a cache controller and an APB peripheral. Each stage states what done means and names the trap people fall into. This app needs JavaScript enabled. Explore:

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