Verilog Contests — Timed RTL and Debug Rounds

Free timed Verilog contests scored ICPC-style: problems solved first, then penalty time. Past rounds can be run virtually on your own clock, so a round you missed is still a round you can take. This app needs JavaScript enabled. Explore:

VLSI Career Roadmap · Course Portal · Verilog Judge · K-Map Solver · Start Module 1