SCL 180 nm Tapeout: RTL-to-GDS Checklist

SCL 180nm tapeout checklist for C2S student teams: process options, die and pad limits, sign-off checks, submission files and a 12-step RTL-to-GDS plan.

By BitForBytes Editorial & Hardware Research Team, Official BitForBytes Hardware Publication · 2026-10-09 · 12 min read

⚡ Quick Summary

An SCL 180 nm tapeout is the submission of a verified GDSII layout for fabrication on the Semi-Conductor Laboratory's 180 nm CMOS process at Mohali, which C2S institutions reach through ChipIN MPW shuttles. The process offers a 1.8 V core and four to six metal layers. Designs are accepted only with clean DRC and antenna reports.

1. Introduction & Core Motivation

First tapeouts often go wrong for reasons that have nothing to do with RTL: a seal ring was missing, the pad ring did not match the package, a reset was never synchronised, or the team discovered chip-level design rules two days before the deadline. None of these show up in simulation, and none are taught in a semester course built around an FPGA board.

Student teams in Chips to Startup (C2S) institutions can now send designs to SCL Mohali through quarterly multi-project wafer (MPW) shuttles run by the ChipIN Centre. The official pages give dates and file requirements, and a detailed public guide to the SCL flow is a 2019 tutorial paper by Joydeep Basu, written from an analog designer's point of view. A digital team needs both sources joined into one sequence with exit criteria.

This article is that sequence: what the process offers, the hard limits on die and pads, a 12-step checklist from RTL freeze to submission, and the specific items that catch first-time teams. After reading, you will be able to plan a digital tapeout backwards from a shuttle date and know what "done" means at every step.

2. Detailed Technical Breakdown

What Does the SCL 180 nm Process Offer?

The SCL 180 nm process offers a 1.8 V CMOS core with optional higher-voltage I/O, up to six aluminium metal layers and analog modules such as MIM capacitors. SCL's own description lists the following.

SCL's MPW schedule page lists the four-metal 1.8 V / 3.3 V option with submission deadlines on the first of January, April, July and October; the six-metal and 5 V options run on a requirement basis. The 2019 tutorial adds what a designer sees in the kit: 1.8 V standard cells for logic, and separate 1.8 V and 3.3 V I/O pad libraries. Note that "180 nm" names the technology generation; individual drawn dimensions in the design rules differ from layer to layer.

What Limits Does a Shuttle Put on Your Chip?

A shuttle limits die size, pad pitch, package pin count and layout grid. These values are from the Shuttle-II page on c2s.gov.in.

Pad count is bounded by the perimeter. For a square die of side S with corner cells of width W_c and pad pitch P:

N_pads ≤ 4 × ⌊ (S - 2W_c) / (P) ⌋

where S, W_c and P are in µm. Worked example: for S = 2000 µm and P = 90 µm, and assuming W_c = 200 µm for illustration, each side holds ⌊ 1600/90 ⌋ = 17 pads, so at most 68. Take the real corner and pad dimensions from the I/O library, and remember that several pads go to core and I/O power and ground before any signal is connected.

What Is the Flow From RTL to GDS?

The flow from RTL to GDS is a chain of transformations, each followed by a check that must pass before the next step starts.

  RTL + testbench
       |  lint, simulation, coverage
       v
  SYNTHESIS  (RTL -> 1.8 V standard cells)  --> equivalence check
       |
       v
  FLOORPLAN  die size, pad ring, power grid, macro placement
       |
       v
  PLACEMENT --> CLOCK TREE SYNTHESIS --> ROUTING
       |                                    |
       |        setup at slow corner        |
       +------- hold at fast corner --------+   (static timing)
       |
       v
  PHYSICAL VERIFICATION
       block-level DRC, LVS, antenna
       |
       v
  CHIP FINISHING
       seal ring, silicon number, dummy fill
       |
       v
  CHIP-LEVEL DRC + antenna (clean)  --> GDSII + checksums + forms
       |
       v
  ChipIN verification report --> fix --> final GDS --> SCL

Timing sign-off uses both ends of the process spread. Setup is checked where cells are slowest and hold where they are fastest:

T_clk ≥ T_clk→q,max + T_comb,max + T_setup - T_skew + T_unc

T_clk→q,min + T_comb,min ≥ T_hold + T_skew

where T_clk is the clock period, T_clk→q the clock-to-Q delay, T_comb the logic delay, T_setup and T_hold the flop requirements, T_skew the capture-minus-launch clock skew and T_unc the clock uncertainty, all in ns. Worked example: for a 50 MHz target, T_clk = 20 ns. With T_clk→q,max = 0.8 ns, T_setup = 0.4 ns, no skew and T_unc = 1.0 ns, the logic may take at most 20 - 0.8 - 0.4 - 1.0 = 17.8 ns at the slow corner. These delay values are illustrative; read the real ones from the SCL Liberty files.

What Is the 12-Step Checklist?

The 12-step checklist below gives each stage one exit criterion, so the team always knows whether it may move on.

Steps 10 and 11 are where a digital team used to block-level work loses time. The 2019 tutorial describes three finishing items for SCL: a seal ring supplied by the foundry and placed around the die, a unique silicon number assigned in advance and placed at the bottom-left of the layout, and dummy fill on the active, poly and metal layers as a final step. It also reports that the full-chip DRC deck enabled more rules than the block-level deck (421 against 356 in the kit version it used). The counts will have changed since 2019; the principle that chip-level DRC is stricter has not.

What Should the RTL and Constraints Look Like Before Synthesis?

Before synthesis, every asynchronous input must be synchronised in RTL and the clock must be fully constrained in SDC. The reset is the input teams most often forget. This module asserts reset immediately and releases it synchronously to the clock.

`default_nettype none
// rst_sync: asynchronous-assert, synchronous-deassert reset.
// Reset: asynchronous, active-low input and output.
// Latency: rst_n_out rises 2 clock edges after rst_n_in rises.
module rst_sync (
    input  wire clk,
    input  wire rst_n_in,    // from the reset pad, asynchronous
    output wire rst_n_out    // safe to use as reset inside the core
);
    reg meta_q;
    reg sync_q;

    always @(posedge clk or negedge rst_n_in) begin
        if (!rst_n_in) begin
            meta_q <= 1'b0;    // assert at once, no clock needed
            sync_q <= 1'b0;
        end else begin
            meta_q <= 1'b1;    // release ripples through two flops
            sync_q <= meta_q;
        end
    end

    assign rst_n_out = sync_q;
endmodule
`default_nettype wire

This infers two flip-flops with asynchronous clear and no combinational logic. Without it, the reset pad can release close to a clock edge and different flops leave reset in different cycles. No latch is inferred because both registers are assigned in both branches.

A minimal constraint file for a single-clock chip:

# chip.sdc - starting point for a single-clock digital tapeout
set clk_period 20.0                        ;# 50 MHz target
create_clock -name clk -period $clk_period [get_ports clk_pad]

set_clock_uncertainty -setup 1.0 [get_clocks clk]  ;# pre-CTS budget
set_clock_uncertainty -hold  0.3 [get_clocks clk]

# Board-side timing: 30% of the cycle on each side as a first guess
set io_delay [expr {0.3 * $clk_period}]
set_input_delay  $io_delay -clock clk [get_ports data_in*]
set_output_delay $io_delay -clock clk [get_ports data_out*]

# The reset pad is asynchronous; rst_sync handles it in RTL
set_false_path -from [get_ports rst_n_pad]

The uncertainty and I/O numbers are placeholders to replace with your own budget. Port names such as clk_pad are examples.

What Goes Into the Submission Pack?

The submission pack contains the layout, proof that it is clean, proof that the file is intact, and two forms. The Shuttle-II page lists these items.

Generate both checksums on the exact file you send:

md5sum chip_top.gds  > chip_top.gds.md5
cksum  chip_top.gds  > chip_top.gds.cksum
cat chip_top.gds.md5 chip_top.gds.cksum

The Shuttle-II sequence had five stages: request a silicon number (8 January 2025), submit the two forms, receive ChipIN's verification report (31 January 2025), fix issues, and send the final GDSII (21 February 2025). The design went to the foundry on 28 February 2025, and packaged chips were scheduled for 31 December 2025.

3. Practical Takeaways for Students

• Exam angle: For "explain the ASIC design flow", draw the RTL-to-GDS chain with the check after each step: equivalence after synthesis, STA after routing, DRC, LVS and antenna before GDS. Naming the corner for each timing check, slow for setup and fast for hold, separates a good answer from a list of stages.
• Interview angle: "What did you check before tapeout?" Give the exit criteria: zero DRC, LVS match, antenna clean, setup and hold met at their corners, pad ring matched to package. "What is a seal ring for?" It surrounds the die to protect the circuit from cracks and moisture entering from the saw line.
• Common mistake: Leaving the pad ring and package choice to the end. They fix the die size, the floorplan and the pin order, and they are needed for the tapeout form weeks before the final GDS.
• Try it yourself: Rehearse the whole sequence on open tools with the SkyWater SKY130 PDK in OpenLane, including DRC in Magic and LVS in Netgen, before you receive the SCL kit. Check rst_sync and your core RTL in the BitForBytes Verilog Judge first.

4. Frequently Asked Questions

Can I practise the tapeout flow before my college gets the SCL design kit?

Yes. The SkyWater SKY130 process is open source, has a 1.8 V core like SCL 180 nm, and is supported by the OpenLane flow, which runs Yosys, OpenROAD, Magic and Netgen from RTL to GDSII. Every stage in the 12-step checklist has an equivalent there.

The rule decks, cell libraries and pad cells differ, so nothing you build transfers file for file. The sequence, the reports you read and the mistakes you make do transfer.

What is a silicon number and why is it requested first?

A silicon number is a unique identifier that the foundry assigns to each design on a shuttle and that is drawn on the chip layout. On Shuttle-II it was the first step of the procedure, with a request deadline about six weeks before the final GDS was due.

It comes first because the identifier is part of the layout itself and of the paperwork that follows. A team that has not requested it cannot finish chip-level layout, however clean the core is.

What is the difference between block-level and chip-level DRC?

Block-level DRC checks the core layout against rules that apply to any piece of layout: widths, spacings, enclosures. Chip-level DRC runs on the finished die and adds rules that only make sense for a whole chip, such as layer density, seal-ring and pad rules.

A core that is clean at block level can therefore fail at chip level. Run the chip-level deck as soon as the pad ring exists, not in the final week.

How do I decide the die size for a student design?

Decide die size from the pad count first and the logic area second. Small student designs are usually pad-limited: the perimeter needed for pads at a 90 µm pitch, plus corners, sets a minimum side length even when the logic would fit in a fraction of the area.

Count signal pads, add core and I/O power and ground pairs, check the total against the package, and choose the smallest shuttle size option whose perimeter holds them.

5. References & Further Reading

• J. Basu, "From Design to Tape-out in SCL 180 nm CMOS Integrated Circuit Fabrication Technology", IETE Journal of Education, 2019 (arXiv:1908.10674).
• Semi-Conductor Laboratory, scl.gov.in: "CMOS Process & Fabrication Facility" and "MPW Schedule" pages.
• MeitY C2S portal, c2s.gov.in: SCL MPW Shuttle-II page and MPW Shuttle-VI page (retrieved October 2026).
• Press Information Bureau, "Chips to Start-up (C2S) Programme: Fostering India's Indigenous Chip Design Ecosystem", 18 January 2026.
• The OpenROAD Project and OpenLane documentation; SkyWater SKY130 open-source PDK.